// **************************************************************
// COPYRIGHT(c)2021, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  : field_select 
// Full name    :  
// Time         : 2021 
// Author       : Haoxiaofei 
// Email        : 1531804419@qq.com
// Data         : 
// Version      : V 2.0 
// 
// Abstract     :ctr_field根据maetedata中的表项配置信息选择对应级流表的匹配字段输入
// Called by    :  
// 
// --------------------------------------------------------------------------------
// *******************
// TIMESCALE
// *******************
// 
`timescale 1ns/1ps
// 
// *******************
// INCLUDE
// *******************
// 
// 
// 
// *******************
// INFORMATION
// *******************
// 
// 
// 
// *******************
// DEFINE(s)
// *******************
// 
// 
// 
// *******************
// DEFINE MODULE PORT
// *******************
// 
module field_mux_128(

       input  wire                    clk                      ,
       input  wire                    rst_n                    ,
       input  wire [127  : 0   ]      ctr_field                ,
       input  wire                    vector_rdy               ,
       input  wire [0   : 1023 ]      pktheader_vector         ,
       output reg                     select_end_o             ,
       output reg  [127  : 0   ]      match_field                               

);
// *******************
// DEFINE LOCAL PARAMETER
// *******************
// 
// 
// 
// *******************
// INNER SIGNAL DECLARATION
// *******************
// REGS
// 
reg vector_rdy_ff1;
reg vector_rdy_ff2;
// 
// WIRES
//field_buffer64
wire [127:0] field_buffer;
//ctr_field
wire [7 : 0] ctr_field0;
wire [7 : 0] ctr_field1;
wire [7 : 0] ctr_field2;
wire [7 : 0] ctr_field3;
wire [7 : 0] ctr_field4;
wire [7 : 0] ctr_field5;
wire [7 : 0] ctr_field6;
wire [7 : 0] ctr_field7;
wire [7 : 0] ctr_field8;
wire [7 : 0] ctr_field9;
wire [7 : 0] ctr_field10;
wire [7 : 0] ctr_field11;
wire [7 : 0] ctr_field12;
wire [7 : 0] ctr_field13;
wire [7 : 0] ctr_field14;
wire [7 : 0] ctr_field15;
//field_buffer64
wire [7 : 0] field_buffer0;
wire [7 : 0] field_buffer1;
wire [7 : 0] field_buffer2;
wire [7 : 0] field_buffer3;
wire [7 : 0] field_buffer4;
wire [7 : 0] field_buffer5;
wire [7 : 0] field_buffer6;
wire [7 : 0] field_buffer7;
wire [7 : 0] field_buffer8;
wire [7 : 0] field_buffer9;
wire [7 : 0] field_buffer10;
wire [7 : 0] field_buffer11;
wire [7 : 0] field_buffer12;
wire [7 : 0] field_buffer13;
wire [7 : 0] field_buffer14;
wire [7 : 0] field_buffer15;
// 
// 
// *******************
// INSTANTCE MODULE
// *******************

field_mux_1024_128 field_mux0_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field0      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o0   ),
          .field_buffer_128_o(field_buffer0   )    
);
field_mux_1024_128 field_mux1_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field1      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o1   ),
          .field_buffer_128_o(field_buffer1   )    
);
field_mux_1024_128 field_mux2_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field2      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o2   ),
          .field_buffer_128_o(field_buffer2   )    
);
field_mux_1024_128 field_mux3_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field3      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o3   ),
          .field_buffer_128_o(field_buffer3   )    
);
field_mux_1024_128 field_mux4_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field4      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o4   ),
          .field_buffer_128_o    (field_buffer4   )    
);
field_mux_1024_128 field_mux5_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field5      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o5   ),
          .field_buffer_128_o    (field_buffer5   )    
);
field_mux_1024_128 field_mux6_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field6      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o6   ),
          .field_buffer_128_o    (field_buffer6   )    
);
field_mux_1024_128 field_mux7_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field7      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o7   ),
          .field_buffer_128_o    (field_buffer7   )    
);
field_mux_1024_128 field_mux8_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field8      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o8   ),
          .field_buffer_128_o(field_buffer8   )    
);
field_mux_1024_128 field_mux9_1024_128(
          .clk               (clk             ),
          .rst_n             (rst_n           ),
          .ctr_field         (ctr_field9      ),
          .vector_rdy        (vector_rdy      ),
          .pktheader_vector  (pktheader_vector),
          // .select_end_o      (select_end_o9   ),
          .field_buffer_128_o(field_buffer9   )    
);
field_mux_1024_128 field_mux10_1024_128(
          .clk               (clk              ),
          .rst_n             (rst_n            ),
          .ctr_field         (ctr_field10      ),
          .vector_rdy        (vector_rdy       ),
          .pktheader_vector  (pktheader_vector ),
          // .select_end_o      (select_end_o10   ),
          .field_buffer_128_o(field_buffer10   )    
);
field_mux_1024_128 field_mux11_1024_128(
          .clk               (clk              ),
          .rst_n             (rst_n            ),
          .ctr_field         (ctr_field11      ),
          .vector_rdy        (vector_rdy       ),
          .pktheader_vector  (pktheader_vector ),
          // .select_end_o      (select_end_o11   ),
          .field_buffer_128_o(field_buffer11   )    
);
field_mux_1024_128 field_mux12_1024_128(
          .clk               (clk              ),
          .rst_n             (rst_n            ),
          .ctr_field         (ctr_field12      ),
          .vector_rdy        (vector_rdy       ),
          .pktheader_vector  (pktheader_vector ),
          // .select_end_o      (select_end_o12   ),
          .field_buffer_128_o    (field_buffer12   )    
);
field_mux_1024_128 field_mux13_1024_128(
          .clk               (clk              ),
          .rst_n             (rst_n            ),
          .ctr_field         (ctr_field13      ),
          .vector_rdy        (vector_rdy       ),
          .pktheader_vector  (pktheader_vector ),
          // .select_end_o      (select_end_o13   ),
          .field_buffer_128_o    (field_buffer13   )    
);
field_mux_1024_128 field_mux14_1024_128(
          .clk               (clk              ),
          .rst_n             (rst_n            ),
          .ctr_field         (ctr_field14      ),
          .vector_rdy        (vector_rdy       ),
          .pktheader_vector  (pktheader_vector ),
          // .select_end_o      (select_end_o14   ),
          .field_buffer_128_o    (field_buffer14   )    
);
field_mux_1024_128 field_mux15_1024_128(
          .clk               (clk              ),
          .rst_n             (rst_n            ),
          .ctr_field         (ctr_field15      ),
          .vector_rdy        (vector_rdy       ),
          .pktheader_vector  (pktheader_vector ),
          // .select_end_o      (select_end_o15   ),
          .field_buffer_128_o    (field_buffer15   )    
);
// *******************
// MAIN CORE
// *******************
//
assign ctr_field0  = ctr_field[127 : 120];
assign ctr_field1  = ctr_field[119 : 112];
assign ctr_field2  = ctr_field[111 : 104];
assign ctr_field3  = ctr_field[103 :  96];
assign ctr_field4  = ctr_field[95  :  88];
assign ctr_field5  = ctr_field[87  :  80];
assign ctr_field6  = ctr_field[79  :  72];
assign ctr_field7  = ctr_field[71  :  64];
assign ctr_field8  = ctr_field[63  :  56];
assign ctr_field9  = ctr_field[55  :  48];
assign ctr_field10 = ctr_field[47  :  40];
assign ctr_field11 = ctr_field[39  :  32];
assign ctr_field12 = ctr_field[31  :  24];
assign ctr_field13 = ctr_field[23  :  16];
assign ctr_field14 = ctr_field[15  :   8];
assign ctr_field15 = ctr_field[7   :   0];


assign field_buffer = {field_buffer0, field_buffer1, field_buffer2, field_buffer3,
                       field_buffer4, field_buffer5, field_buffer6, field_buffer7,
                       field_buffer8, field_buffer9, field_buffer10,field_buffer11,
                       field_buffer12,field_buffer13,field_buffer14,field_buffer15
                      };
//第一级CASE
always @(posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
        vector_rdy_ff1   <= 1'b0     ;
    end
    else  begin
        vector_rdy_ff1   <= vector_rdy     ;
    end 
end
//第二级CASE
always @(posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
        vector_rdy_ff2   <= 1'b0     ;
    end
    else  begin
        vector_rdy_ff2   <= vector_rdy_ff1     ;
    end 
end
//REG 输出
always @(posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
        select_end_o   <= 1'b0       ;
        match_field    <= 127'b0     ;
    end
    else if (vector_rdy_ff2) begin
        select_end_o   <= 1'b1          ;
        match_field    <= field_buffer  ;
    end 
    else begin
        select_end_o   <= 1'b0       ;
        match_field    <= 127'b0     ;
    end 
end

endmodule